The present invention relates to a method and apparatus for controlling operations in a vehicle, at least two processors accessing at least one memory means.
German Patent No. 41 29 809 describes a multi-computer system, in particular for controlling operations in motor vehicles, in which at least two computers jointly access one memory means. In order, in the case of multiple computers, to guarantee data transfer security when accessing the same memory, and to minimize delays due to data interchange between the computers, the memory means is divided into at least two regions. The first memory region is accessed by a first computer only in reading fashion and by a second computer only in writing fashion. The second memory region is accessed by the second computer only in reading fashion and by the first computer only in writing fashion. The computers are synchronized in such a way that they access the memory means at the same point in time in the same fashion. Since the two computers are now accessing decoupled memory regions in either reading or writing fashion, a collisionxe2x80x94i.e. a read or write access to the identical address in the memory meansxe2x80x94is prevented. This synchronization can, however, result in undesirable waiting times during program execution.
It is thus evident that the existing art is not capable of providing optimum results in every respect.
The object thus arises, in the context of at least two processors which, in particular, operate independently of one another and which access one memory means, of achieving asynchronous data transfer and the highest possible data throughput, and of optimizing the detection and avoidance of collisions in the event of a simultaneous read and/or write access.
The present invention is based on a method and an apparatus for controlling operations in a vehicle, at least two processors accessing at least one memory means and a simultaneous read and/or write access, in the case of at least two processors, to the identical address of the memory means during program execution being prevented. Advantageously, an address comparison is used, before the actual read and/or write access, to detect the fact that at least two processors are accessing the identical address.
As a function of the address comparison, preferably a first signal is transmitted to the first processor and a second signal to a second processor, and program execution by at least one of the at least two processors is brought to a halt by the respective signal.
Advantageously, because program execution by the at least first of the at least two computers is brought to a halt by the respective signal until different addresses are once again detected in the address comparison and/or until the read and/or write access of the at least second processor is complete, access by the at least two processors to the at least one memory means is decoupled in time.
In an advantageous embodiment, program execution by at least one of the at least two processors is brought to a halt by the respective signal for a time that is definable and/or can be ascertained from the address comparison.
It is furthermore advantageous that the read and/or write accesses of the at least two processors to addresses of the at least one memory means can occur asynchronously, i.e. at any desired points in time.
Advantageously, what serves as the criterion for simultaneous or almost simultaneous access to the identical address in order to determine which processor""s program execution is to be brought to a halt is the identity of the processor which first started the access or the processor by which the address was first transmitted.
The advantageous result of this is to prevent the content read at an address from being invalid.
A cost advantage is thereby obtained on the one hand as compared to the use of synchronous memory means and a device that synchronizes access, and on the other hand as compared to the use of complex hardware circuits, for example additional registers (hardware semaphores) for collision avoidance.
Because both subsystems, in particular both processors, thus asynchronously operate at full performance and exchange data, higher data throughputs can be obtained. The processors operate independently, and access the shared memory means at any desired points in time. The present invention can, of course, also be utilized for synchronized operation of the at least two processors.
An additional interrupt workload or interrupt processing workload as a consequence of computer coupling, i.e. coupling of the two processors, is also advantageously avoided.
Advantageously, the additional run time workload is very small, since a temporal access decoupling occurs only if a conflict is imminent, which occurs very seldom. This guarantees that the data in the memory are as up-to-date as possible.